The next wave of AI silicon may pivot from today's compute-heavy architectures to memory-centric ones optimized for inference. This fundamental shift would allow high-performance chips to be produced on older, more accessible 7-14nm manufacturing nodes, disrupting the current dependency on cutting-edge fabs.

For companies like NVIDIA or Google, moving from TSMC to Intel or Samsung is not a simple supplier switch. It necessitates a complete redesign of the chip's architecture to fit the new foundry's technology. This complex and costly process can take one to two years, making it a last resort.

Apple crushed competitors by creating its M-series chips, which delivered superior performance through tight integration with its software. Tesla is following this playbook by designing its own AI chips, enabling a cohesive and hyper-efficient system for its cars and robots.

Musk states that designing the custom AI5 and AI6 chips is his 'biggest time allocation.' This focus on silicon, promising a 40x performance increase, reveals that Tesla's core strategy relies on vertically integrated hardware to solve autonomy and robotics, not just software.

TSMC's "pure-play foundry" model, where it only manufactures chips and doesn't design its own, builds deep trust. Customers like Apple and NVIDIA can share sensitive designs without fear of competition, unlike with rivals Intel and Samsung who have their own chip products.

For its next-generation V7 TPU AI chip, Google is diversifying its supply chain. It's retaining incumbent Broadcom for the complex 'training' version while bringing in low-cost entrant Mediatek for the 'inference' version. This sophisticated strategy mitigates supply risk while keeping critical IP with a trusted partner.

Tesla's decision to stop developing its Dojo training supercomputer is not a failure. It's a strategic shift to focus on designing hyper-efficient inference chips for its vehicles and robots. This vertical integration at the edge, where real-world decisions are made, is seen as more critical than competing with NVIDIA on training hardware.

Beyond the simple training-inference binary, Arm's CEO sees a third category: smaller, specialized models for reinforcement learning. These chips will handle both training and inference, acting like 'student teachers' taught by giant foundational models.

At a massive scale, chip design economics flip. For a $1B training run, the potential efficiency savings on compute and inference can far exceed the ~$200M cost to develop a custom ASIC for that specific task. The bottleneck becomes chip production timelines, not money.