The physical area a multiplier circuit requires on a chip grows quadratically with the number of bits (e.g., p*q). This non-linear scaling is the fundamental reason why lower-precision formats like FP4 and FP8 offer disproportionately large performance and efficiency gains for AI workloads compared to a linear improvement.

Since the weight matrix in a systolic array is reused many times, it doesn't need to be loaded quickly. Chip designers can use slow, low-bandwidth connections to "trickle feed" the weights, minimizing the required wiring and thus saving precious die area. This prioritizes area efficiency over initial load latency.

Existing AI chips force a trade-off: high-throughput HBM memory (NVIDIA, Google) has high latency, while low-latency SRAM memory (Grok) has poor throughput. MatX's architecture combines both, putting model weights in fast SRAM and inference data in high-capacity HBM to achieve both low latency and high throughput.

The necessity of batching stems from a fundamental hardware reality: moving data is far more energy-intensive than computing with it. A single parameter's journey from on-chip SRAM to the multiplier can cost 1000x more energy than the multiplication itself. Batching amortizes this high data movement cost over many computations.

Unlike competitors, MatX's ML team conducts fundamental research, training LLMs to validate novel hardware choices. This allows them to safely "cut corners" on industry standards, such as using less precise rounding methods. This deep co-design of model and hardware creates a uniquely efficient product.

The plateauing performance-per-watt of GPUs suggests that simply scaling current matrix multiplication-heavy architectures is unsustainable. This hardware limitation may necessitate research into new computational primitives and neural network designs built for large-scale distributed systems, not single devices.

Martin Shkreli makes a case for photonic computing—using light instead of electrons—as the next major paradigm in AI hardware. He argues that because matrix multiplications (95% of a GPU's job) are a natural function of light interference, photonic chips could offer an "insane speedup" with O-of-one complexity, making them a potential successor to GPUs.

Systolic arrays (like NVIDIA's Tensor Cores) overcome the high cost of data movement by storing the large, reusable weight matrix directly within the compute fabric. This avoids repeatedly fetching weights from a distant register file, dramatically improving the ratio of computation to communication.

OpenAI is designing its custom chip for flexibility, not just raw performance on current models. The team learned that major 100x efficiency gains come from evolving algorithms (e.g., dense to sparse transformers), so the hardware must be adaptable to these future architectural changes.