The performance gains from Nvidia's Hopper to Blackwell GPUs come from increased size and power, not efficiency. This signals a potential scaling limit, creating an opportunity for radically new hardware primitives and neural network architectures beyond today's matrix-multiplication-centric models.

As performance gains from general-purpose CPUs stalled, the industry shifted to domain-specific architectures (DSAs). By designing hardware like GPUs and TPUs for narrow tasks like AI, architects can achieve dramatic performance improvements that are no longer possible with traditional CPUs.

The plateauing performance-per-watt of GPUs suggests that simply scaling current matrix multiplication-heavy architectures is unsustainable. This hardware limitation may necessitate research into new computational primitives and neural network designs built for large-scale distributed systems, not single devices.

The GPU architecture is economically optimized for slow AI inference, offering a very low cost per token. However, this efficiency plummets when speed is required, as the cost and power per token increase exponentially, creating a market for alternative architectures in high-speed applications.

Modern high-performance compute infrastructure, from GPUs to software stacks, is becoming "LLM-pilled"—designed specifically for large language models. This creates significant inefficiencies for other critical AI domains, like structural biology, that have different computational needs.

A key trend in AI models is "dynamism"—the ability to vary computation and memory usage per token, as seen in Mixture-of-Experts (MoE) architectures. Current hardware, designed before this trend, is inefficient. New chips must be built to accelerate these dynamic computations.

While NVIDIA's GPUs have been the primary AI constraint, the bottleneck is now moving to other essential subsystems. Memory, networking interconnects, and power management are emerging as the next critical choke points, signaling a new wave of investment opportunities in the hardware stack beyond core compute.

The intense power demands of AI inference will push data centers to adopt the "heterogeneous compute" model from mobile phones. Instead of a single GPU architecture, data centers will use disaggregated, specialized chips for different tasks to maximize power efficiency, creating a post-GPU era.

GPUs were designed for graphics, not AI. It was a "twist of fate" that their massively parallel architecture suited AI workloads. Chips designed from scratch for AI would be much more efficient, opening the door for new startups to build better, more specialized hardware and challenge incumbents.