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At chip startup Positron, autonomous reasoning models like GPT-6 Astra and Opus 5.5 manage closed-loop silicon verification on specialized Cadence Palladium emulator systems. Rather than requiring human-written test harnesses, the models independently read documentation, create synthesized cheat sheets, build testing infrastructure, and triage failures, accelerating gate-level hardware verification runs from roughly 10 Hz software simulations to 500 kHz on hardware emulators.

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Unlike previous models that require constant guidance, GPT-5.5 can operate as a long-running, autonomous agent. It worked for nearly six hours on a complex data migration task, requiring virtually no human intervention to identify issues, propose solutions, and implement them successfully.

The significant leap in LLMs isn't just better text generation, but their ability to autonomously execute complex, sequential tasks. This 'agentic behavior' allows them to handle multi-step processes like scientific validation workflows, a capability earlier models lacked, moving them beyond single-command execution.

Unlike competitors, MatX's ML team conducts fundamental research, training LLMs to validate novel hardware choices. This allows them to safely "cut corners" on industry standards, such as using less precise rounding methods. This deep co-design of model and hardware creates a uniquely efficient product.

The future of hardware testing involves moving beyond simple, sequential pass/fail checks. AI test agents will instead explore a system's state space, intelligently choosing the next test point that will yield the most new information, a concept called 'knowledge maximizing.'

Designing a chip is not a monolithic problem that a single AI model like an LLM can solve. It requires a hybrid approach. While LLMs excel at language and code-related stages, other components like physical layout are large-scale optimization problems best solved by specialized graph-based reinforcement learning agents.

An "agent harness" is the software that translates an LLM's token outputs into actions—the body for the brain. Model providers like Anthropic now tightly couple their models to proprietary harnesses (e.g., Opus 4.8 to Claude Code) via reinforcement learning, making the model self-aware of its environment to boost performance.

Historically, a major barrier for new AI chips was the software effort to support new models. Now, AI agents can automate this porting process. Positron AI was able to get Muse's Glimmer model running on their custom hardware in hours, not months, drastically lowering the barrier to entry.

The rise of agent orchestration using specialized, open-source models will drive demand for custom ASICs. Jerry Murdock argues that putting a model on a dedicated chip will be far cheaper and more tunable for specific workloads than using expensive, general-purpose GPUs like Nvidia's, spurring a hardware shift.

Contrary to popular belief, the longest phase in the 24-36 month chip development cycle isn't the architectural design. It's the verification, validation, and debugging phase. This is where AI tools are providing the most significant productivity gains for engineers.

Hardware development is shifting from slow, manual verification cycles (every 6-12 months) to a continuous model powered by AI. Tools like Flow Engineering allow engineers to see the ripple effects of a small design change across an entire complex system (like a rocket) in real-time, mirroring the CI/CD paradigm of software.