Get your free personalized podcast brief

We scan new podcasts and send you the top 5 insights daily.

The key metric for AI chips (GPUs/TPUs) is achieving a high percentage of theoretical peak performance (e.g., 70-80%). This concept, known as "mechanical sympathy," is largely absent in the CPU world, where software performance is so inefficient that measuring against peak is considered nonsensical.

Related Insights

The standard for measuring large compute deals has shifted from number of GPUs to gigawatts of power. This provides a normalized, apples-to-apples comparison across different chip generations and manufacturers, acknowledging that energy is the primary bottleneck for building AI data centers.

The performance gains from Nvidia's Hopper to Blackwell GPUs come from increased size and power, not efficiency. This signals a potential scaling limit, creating an opportunity for radically new hardware primitives and neural network architectures beyond today's matrix-multiplication-centric models.

Nvidia dominates AI because its GPU architecture was perfect for the new, highly parallel workload of AI training. Market leadership isn't just about having the best chip, but about having the right architecture at the moment a new dominant computing task emerges.

When power (watts) is the primary constraint for data centers, the total cost of compute becomes secondary. The crucial metric is performance-per-watt. This gives a massive pricing advantage to the most efficient chipmakers, as customers will pay anything for hardware that maximizes output from their limited power budget.

A GPU is like a truck: its value is the massive payload (parallel data processing), not the driver (control logic). It excels at going straight for a long time. A CPU is like a motorcycle: it's mostly driver, designed for agility and complex steering through obstacle courses (branching instructions).

Model architecture decisions directly impact inference performance. AI company Zyphra pre-selects target hardware and then chooses model parameters—such as a hidden dimension with many powers of two—to align with how GPUs split up workloads, maximizing efficiency from day one.

GPUs were designed for graphics, not AI. It was a "twist of fate" that their massively parallel architecture suited AI workloads. Chips designed from scratch for AI would be much more efficient, opening the door for new startups to build better, more specialized hardware and challenge incumbents.

Instead of using high-level compilers like Triton, elite programmers design algorithms based on specific hardware properties (e.g., AMD's MI300X). This bottom-up approach ensures the code fully exploits the hardware's strengths, a level of control often lost through abstractions like Triton.

Efficiency gains in new chips like NVIDIA's H200 don't lower overall energy use. Instead, developers leverage the added performance to build larger, more complex models. This "ambition creep" negates chip-level savings by increasing training times and data movement, ultimately driving total system power consumption higher.

The current 2-3 year chip design cycle is a major bottleneck for AI progress, as hardware is always chasing outdated software needs. By using AI to slash this timeline, companies can enable a massive expansion of custom chips, optimizing performance for many at-scale software workloads.