While competitors chased cutting-edge physics, AI chip company Groq used a more conservative process technology but loaded its chip with on-die memory (SRAM). This seemingly less advanced but different architectural choice proved perfectly suited for the "decode" phase of AI inference, a critical bottleneck that led to its licensing deal with NVIDIA.

Unlike competitors, MatX's ML team conducts fundamental research, training LLMs to validate novel hardware choices. This allows them to safely "cut corners" on industry standards, such as using less precise rounding methods. This deep co-design of model and hardware creates a uniquely efficient product.

While NVIDIA's GPUs have been the primary AI constraint, the bottleneck is now moving to other essential subsystems. Memory, networking interconnects, and power management are emerging as the next critical choke points, signaling a new wave of investment opportunities in the hardware stack beyond core compute.

NVIDIA's commitment to CUDA's backward compatibility prevents it from making fundamental changes to its chip architecture. This creates an opportunity for new players like MatX to build chips from a blank slate, optimized purely for modern LLM workloads without being tied to a decade-old programming model.

Top-tier kernels like FlashAttention are co-designed with specific hardware (e.g., H100). This tight coupling makes waiting for future GPUs an impractical strategy. The competitive edge comes from maximizing the performance of available hardware now, even if it means rewriting kernels for each new generation.

Model architecture decisions directly impact inference performance. AI company Zyphra pre-selects target hardware and then chooses model parameters—such as a hidden dimension with many powers of two—to align with how GPUs split up workloads, maximizing efficiency from day one.

GPUs were designed for graphics, not AI. It was a "twist of fate" that their massively parallel architecture suited AI workloads. Chips designed from scratch for AI would be much more efficient, opening the door for new startups to build better, more specialized hardware and challenge incumbents.

Instead of using high-level compilers like Triton, elite programmers design algorithms based on specific hardware properties (e.g., AMD's MI300X). This bottom-up approach ensures the code fully exploits the hardware's strengths, a level of control often lost through abstractions like Triton.

The popular PyTorch Profiler only shows the 'tip of the iceberg.' To achieve meaningful performance gains, engineers must move beyond it and analyze 50-60 low-level GPU metrics related to streaming multiprocessors, instruction pipelines, and specialized function units. Most of the PyTorch community stops too early.