In the current supply-constrained market, the most critical question from customers is immediate availability. This allows new chip startups to gain market traction by designing architectures that avoid common bottlenecks like HBM and advanced packaging, even if it means sacrificing peak performance for speed to market.

Despite massive financial incentives, high-frequency trading firms rarely develop custom ASICs. CZ explains that FPGAs offer the best trade-off between speed and flexibility. Trading algorithms change too frequently, making the long development cycle of custom silicon impractical compared to reprogrammable FPGAs.

Etched uses a strategy called "prefetching" to compress timelines. Before their silicon arrived, they built racks with mock thermal chips and ran their full software stack on FPGAs. This ensured everything was ready the moment the real chips landed, collapsing their bring-up time.

True co-design between AI models and chips is currently impossible due to an "asymmetric design cycle." AI models evolve much faster than chips can be designed. By using AI to drastically speed up chip design, it becomes possible to create a virtuous cycle of co-evolution.

Historically, a major barrier for new AI chips was the software effort to support new models. Now, AI agents can automate this porting process. Positron AI was able to get Muse's Glimmer model running on their custom hardware in hours, not months, drastically lowering the barrier to entry.

The most significant aspect of OpenAI's Jalapeno chip isn't its performance but its rapid nine-month 'tape out' time. This demonstrates that using AI models to design hardware can dramatically shorten development cycles, creating a new competitive advantage based on iteration speed.

For a $1B training run, the subsequent inference costs will exceed $1B. A custom ASIC could save over 20% ($200M+), which is enough to fund the chip's tape-out. This shifts the hardware bottleneck from manufacturing cost to development timeline.

The current 2-3 year chip design cycle is a major bottleneck for AI progress, as hardware is always chasing outdated software needs. By using AI to slash this timeline, companies can enable a massive expansion of custom chips, optimizing performance for many at-scale software workloads.

Startups building custom silicon for physical autonomy face immense capital costs. A staged approach can de-risk this by first developing and selling a hardware-agnostic software layer for model optimization. This generates early revenue, proves the market, and funds the gradual progression towards a full custom ASIC tape-out.