Existing AI chips force a trade-off: high-throughput HBM memory (NVIDIA, Google) has high latency, while low-latency SRAM memory (Grok) has poor throughput. MatX's architecture combines both, putting model weights in fast SRAM and inference data in high-capacity HBM to achieve both low latency and high throughput.

Unlike past cycles driven solely by new demand (e.g., mobile phones), the current AI memory super cycle is different. The new demand driver, HBM, actively constrains the supply of traditional DRAM by competing for the same limited wafer capacity, intensifying and prolonging the shortage.

Cerebras overcame the key obstacle to wafer-scale computing—chip defects—by adopting a strategy from memory design. Instead of aiming for a perfect wafer, they built a massive array of identical compute cores with built-in redundancy, allowing them to simply route around any flaws that occur during manufacturing.

AI workloads are limited by memory bandwidth, not capacity. While commodity DRAM offers more bits per wafer, its bandwidth is over an order of magnitude lower than specialized HBM. This speed difference would starve the GPU's compute cores, making the extra capacity useless and creating a massive performance bottleneck.

The next wave of AI silicon may pivot from today's compute-heavy architectures to memory-centric ones optimized for inference. This fundamental shift would allow high-performance chips to be produced on older, more accessible 7-14nm manufacturing nodes, disrupting the current dependency on cutting-edge fabs.

NVIDIA's approach requires connecting thousands of Grok chips, creating latency bottlenecks. Cerebras's CEO argues its single, integrated wafer-scale system avoids this "interconnect tax," offering superior memory bandwidth and performance for massive models by eliminating the wiring between thousands of tiny chips.

While NVIDIA's GPUs have been the primary AI constraint, the bottleneck is now moving to other essential subsystems. Memory, networking interconnects, and power management are emerging as the next critical choke points, signaling a new wave of investment opportunities in the hardware stack beyond core compute.

Andrew Feldman, CEO of competitor Cerebras, argues their single wafer-scale chip is superior for large AI models. He contends that connecting thousands of smaller GPUs, as Nvidia does, introduces significant latency from physical wiring that negates on-paper performance specs, creating a fundamental bottleneck.

The primary bottleneck for AI inference is now memory (HBM), not compute. To circumvent this, industry giants Nvidia and AWS are making multi-billion dollar deals for systems from Groq and Cerebrus that use on-chip SRAM, which is faster and not subject to the same supply constraints.